Phase-locked loop (PLL) circuits are well known and are often used for frequency multiplication purposes. The main components of a PLL circuit, as shown in FIG. 1, comprise a phase detector/comparator, a loop filter (LPF), and a voltage-controlled oscillator (VCO). Typically, a PLL circuit is designed to generate an output clock signal at twice the frequency (2f) of an input clock signal (f). However, it is also generally desirable for a clock signal to have a 50% duty cycle (symmetrical square wave). In order to ensure a 50 percent duty cycle for the output clock signal (2f) in the PLL circuit of FIG. 1, the VCO is operated at 4 times f, and a divide-by-2 counter is used to provide the 2f output at a 50% duty cycle. In addition, a divide-by-4 counter is needed in the feedback loop to provide a correct frequency comparison with the input clock f in the phase detector. While this PLL design approach offers flexibility for frequency multiplication, it does have at least two significant disadvantages:
(1) increased power consumption due to the VCO operation at 4X frequency; and PA1 (2) complex analog design of the VCO circuit, including techniques for reducing power noise and frequency jitter.
Various types of improved VCO circuits have been disclosed in the prior art. For example, in U.S. Pat. No. 5,061,907 issued to R. R. Rasmussen, a multi-stage ring oscillator with ring trip-point compensation is used to control the duty cycle of the VCO output.
In U.S. Pat. No. 5,081,428 issued to A. H. Atriss et al., a VCO circuit is disclosed which uses current mirrors to generate a 50 percent duty cycle output which is derived directly from the VCO frequency. Therefore, there is no need to operate the VCO at 4 times the frequency of the input clock signal, as in the prior art circuit shown in FIG. 1. This improved VCO can be used in a 2X PLL circuit as shown in FIG. 2. While the operating frequency of this VCO circuit has been reduced to half the frequency of the prior art circuit shown in FIG. 1, the VCO circuit design is complex and challenging.
Another prior art method for doubling the incoming clock frequency is through the use of an exclusive OR (XOR) gate, as shown in FIG. 3. An incoming clock signal is connected to the first input of the XOR gate, and is also connected to the second input through a delay element. If the input clock has a 50% duty cycle, the output will be a clock at twice the input frequency. However, the duty cycle of this output frequency can vary between 20 percent and 80 percent. For example, if the delay element provides a nominal delay of 40 percent of the output clock period, the process variations in manufacturing the delay element can result in a delay which is as small as one half (20%), or as large as two times (80%), the nominal 40 percent delay. A 20 percent worst case duty cycle clock is unacceptable for most applications, and effectively prohibits further multiplication. Therefore, there is still a need for a simplified and improved circuit and method for frequency multiplication, with an equalized (50%) duty cycle output.
Accordingly, it is an object of the present invention to overcome the disadvantages of the prior art, and to provide a simplified frequency multiplication circuit with a stable 50% duty cycle output.